[A Hardware Architecture for Surface Splatting]

A Hardware Architecture for Surface Splatting

Tim Weyrich1,2,  Simon Heinzle1,  Timo Aila3,4,  Daniel B. Fasnacht1,  Stephan Oetiker1,  Mario Botsch1,  Cyril Flaig1,  Simon Mall1,  Kaspar Rohrer1,  Norbert Felber1,  Hubert Kaeslin1,  Markus Gross1

1 ETH Zurich
2 Princeton University
3 Helsinki University of Technology
4 NVIDIA Research

Abstract

We present a novel architecture for hardware-accelerated rendering of point primitives. Our pipeline implements a refined version of EWA splatting, a high quality method for antialiased rendering of point sampled representations. A central feature of our design is the seamless integration of the architecture into conventional, OpenGL-like graphics pipelines so as to complement triangle-based rendering. The specific properties of the EWA algorithm required a variety of novel design concepts including a ternary depth test and using an on-chip pipelined heap data structure for making the memory accesses of splat primitives more coherent. In addition, we developed a computationally stable evaluation scheme for perspectively corrected splats. We implemented our architecture both on reconfigurable FPGA boards and as an ASIC prototype, and we integrated it into an OpenGL-like software implementation. Our evaluation comprises a detailed performance analysis using scenes of varying complexity.

Citation Style:    Publication

A Hardware Architecture for Surface Splatting.
Tim Weyrich, Simon Heinzle, Timo Aila, Daniel B. Fasnacht, Stephan Oetiker, Mario Botsch, Cyril Flaig, Simon Mall, Kaspar Rohrer, Norbert Felber, Hubert Kaeslin, Markus Gross.
In ACM Transactions on Graphics (Proc. SIGGRAPH), 26, 3 (Jul. 2007), 90:1–90:11, Los Angeles, CA, 2007.
Tim Weyrich, Simon Heinzle, Timo Aila, Daniel Fasnacht, Stephan Oetiker, Mario Botsch, Cyril Flaig, Simon Mall, Kaspar Rohrer, Norbert Felber, Hubert Kaeslin, and Markus Gross. A hardware architecture for surface splatting. ACM Trans. on Graphics (Proc. SIGGRAPH 2007), 26(3):90:1–90:11, 2007.Weyrich, T., Heinzle, S., Aila, T., Fasnacht, D., Oetiker, S., Botsch, M., Flaig, C., Mall, S., Rohrer, K., Felber, N., Kaeslin, H., and Gross, M. 2007. A hardware architecture for surface splatting. ACM Trans. on Graphics (Proc. SIGGRAPH 2007) 26, 3, 90:1–90:11.T. Weyrich, S. Heinzle, T. Aila, D. Fasnacht, S. Oetiker, M. Botsch, C. Flaig, S. Mall, K. Rohrer, N. Felber, H. Kaeslin, and M. Gross, “A hardware architecture for surface splatting,” ACM Trans. on Graphics (Proc. SIGGRAPH 2007), vol. 26, no. 3, pp. 90:1–90:11, 2007.

Acknowledgments

Many thanks go to Matthias Bra ̈ndli for the back-end design of the ASIC and to Hanspeter Mathys for his support with the ASIC board production. Tomas Akenine-Mo ̈ller for helpful suggestions with the text. This research has partly been supported by a grant from the Department of Computer Science, ETH Zurich. FPU IP cores were donated by Arithmatica Inc.


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